This invention relates generally to oscillation circuits and more particularly to a system for selecting the duty cycle of a digital voltage signal.
Oscillator circuits are used to generate timing signals that synchronize digital circuitry. One crystal oscillator circuit that uses metal oxide semiconductor (MOS) technology is the Pierce oscillator. Pierce oscillators are well known to those skilled in the art and are described in detail in: "Crystal Oscillator's Using HCMOS ICs", Synetics Data Book 1986. Pierce oscillators are also described in U.S. Pat. No. 4,383,244 to Saari which is hereby incorporated by reference.
The Pierce oscillator generates a repetitive signal from a crystal that is then amplified with an invertor. The invertor generates a clock signal with different digital logic levels for synchronizing digital logic circuitry. The invertor has a large gain to accurately detect small changes in the crystal output voltage. However, with a high gain invertor, it is critical that the transistor circuitry in the invertor be evenly matched to provide clock signals with a consistent duty cycle.
Present oscillators, such as the Pierce oscillator described above, have difficulty providing a consistent duty cycle for different integrated circuit (IC) components. For example, due to process variations, two ICs with the same oscillator circuit design may generate clock signals with different duty cycles. A process mismatch between a first and second FET (typically used to create an invertor) can significantly change the duty cycle of the oscillator circuit output. Thus, minor process variations on different IC wafers or even different IC chips on the same wafer can alter the characteristics of the clock signal.
It is also difficult to effectively modify clock frequencies without also having to recalculate the process parameters for every component in the oscillation circuit. For example, a 16 MHz crystal, known as a fundamental crystal, may have an inherent 50% duty cycle with a given invertor. A 50% duty cycle (50/50 duty cycle) is a signal that is a logic one for the first half of a clock period and logic zero for the second half of the clock period. However, a 32 MHz crystal, known as an overtone crystal, oscillates on the third harmonic. While the 16 MHz crystal may generate the desired 50/50 duty cycle, the 32 MHz crystal may create a different duty cycle with the same amplifier.
In addition, each digital circuit can have varying duty cycle requirements. For example, a first oscillation circuit may require a 50/50 duty cycle while a second circuit may require a 60/40 duty cycle. Having to redesign the oscillator circuit and accordingly the transistor process parameters, such as channel length and channel width, for each required oscillation frequency and duty cycle, increases design time and cost. In addition, due to integrated circuit (IC) process variations, as described above, the oscillator circuit may still not operate as originally designed.
Accordingly, a need remains for an oscillator circuit that provides a clock signal with a consistent duty cycle over a wide range of IC process parameters and operating frequencies.